> Complete documentation index: [llms.txt](/llms.txt). Markdown versions of all pages are available by appending `.md` to page URLs.

# Binho Atira: Hardware reference

> Connectors and pinout, target power, UART bridge and specifications of the Binho Atira.

Connectors, pinout, target power, the UART bridge and specifications of the Binho Atira.

## Connectors

The Atira has three target connectors:

* **J4**: 10-pin, 1.27 mm debug header. SWD and SPI.
* **J3**: 3-pin UART bridge header.
* **J2**: second UART bridge header (same signals as J3) plus the target rail.

### J4 debug header

| Pin | Signal | Pin | Signal |
| --- | ------ | --- | ------ |
| 1 | VDD (target rail) | 2 | SWDIO |
| 3 | GND | 4 | SWCLK |
| 5 | GND | 6 | SWO (not used in firmware 1.0) |
| 7 | key | 8 | TDI (not used in firmware 1.0) |
| 9 | TRST | 10 | nRESET |

Use a straight (not mirrored) 10-pin Cortex debug cable: pin 1 to pin 1 at both ends.

:::caution
Pin 9 is `TRST`, not the GNDDetect pin of the standard Cortex debug pinout. A cable or target that grounds pin 9 is fine for SWD, but SPI uses pin 9 as its chip select.

:::

### J4 as an SPI flash header

SPI uses J4 with its own pin assignment. The SWD signal names do not apply.

| Flash pin (25-series NOR) | J4 pin |
| ------------------------- | ------ |
| /CS | 9 |
| CLK | 4 |
| DI (MOSI) | 6 |
| DO (MISO) | 8 |
| VCC | 1 (target rail) |
| GND | 3 |
| /WP, /HOLD | tie to VCC |

The native chip select is `CS_2`. The SPI clock goes up to **8 MHz**; the firmware refuses a higher clock.

:::caution
Do not run SPI while an SWD target is connected to J4. The SPI chip select drives pin 9, which some debug targets tie to ground.

:::

### J3 and J2 UART bridge

| Signal | J3 | J2 |
| ------ | -- | -- |
| TX (from the probe, to the target's RX) | 1 | 4 |
| GND | 2 | 1 |
| RX (to the probe, from the target's TX) | 3 | 5 |
| Target rail | None | 3 |

:::danger
J2 pin 3 is the target rail. A wire from J2 pin 3 to a target GPIO feeds 3.3 V into that pin.

:::

## Target power

The probe supplies 3.3 V on J4 pin 1 (and J2 pin 3). The rail is off when the probe powers up. It stays in the state last set until it is changed or the probe is unplugged.

The probe's level shifters on J2, J3 and J4 run from the same rail. **Switch the rail on before any SWD, SPI or UART traffic**, even when the target has its own supply. With the rail off, SWD fails to connect and the UART bridge passes no data.

The probe measures the rail: voltage in mV, current in µA and power in mW. A reading taken right after switching lags by about 0.5 s.

:::danger
Self-powered targets are not supported in 9.0. Power the target from Atira. A self-powered board works only if it is a 3.3 V board with J4 pin 1 unwired. Power it before turning Atira supply on, and turn Atira supply off before unplugging or swapping it.

:::

## UART bridge

The bridge appears as a serial port: `/dev/ttyACM*` on Linux, `/dev/cu.usbmodem*` on macOS, `COMx` on Windows. Open it with any terminal or serial library. The probe uses the baud rate and line settings the program sets when it opens the port.

Verified baud rates: 300, 600, 1200, 9600 and 115200, byte-exact on Atira firmware 1.0.

To find which serial port belongs to which probe, ask the SDK (see [UART bridge port](/hardware/atira/protocols/#uart-bridge-port)).

## Specifications

| | |
| --- | --- |
| Host interface | USB-C, USB ID `1fc9:8347` |
| Probe MCU | NXP MCX A156 (Arm Cortex-M33) |
| Firmware | Atira firmware 1.0.x |
| Debug | SWD, Arm Cortex-M; CMSIS-DAP compatible (pyOCD) |
| Hardware breakpoints | Yes (Cortex-M FPB) |
| Target rail | 3.3 V, on/off, on J4 pin 1 and J2 pin 3 |
| Rail measurement | Voltage (mV), current (µA), power (mW) |
| SPI | Controller, up to 8 MHz, chip select `CS_2` on J4 pin 9 |
| SPI flash programming | 25-series NOR: detect, read, erase, program, verify (read-back or on-probe CRC-32) |
| SPI flash program speed | About 154 KiB/s over the USB bulk interface (Linux, W25Q128JV) |
| UART bridge | USB CDC serial port, 300, 600, 1200, 9600, 115200 baud verified |
| Connectors | J4 10-pin 1.27 mm debug header; J3 3-pin UART; J2 UART + rail |